1. Field Of The Invention
This invention relates generally to high density integrated circuit memories of the electrically erasable 0 programmable read-only memory (EEPROM) type and more particularly EEPROM arrays of the flash memory type which may be either flash erased or erased on the basis of one or more sectors.
2. Description Of Related Art
Flash memory arrays are known in the prior art and typically are comprised of an arrangement of single transistors cells which are connected together in such a way that read/write non-volatile storage is achieved. Typical flash memory arrays of the prior art are completely erased with one erase cycle, or in other embodiments erased entirely with two erase cycles. FIGS. 1 and 2, which will be described more fully hereinafter, illustrate typical prior art EEPROM flash memory array circuits.
FIG. 1 illustrates, in abbreviated schematic form, a prior art flash memory array 1 which utilizes single transistor cells at the intersection word lines and bit lines. More particularly, referring to FIG. 1 transistor M0,0 is positioned at the intersection of word line WL0 and the bit line BL0; transistor M0,l is positioned at the intersection of word line WL0 and bit line BL1; and similarly transistor M0,2 is positioned at intersection word line of WL0 and bit line BLl. Similarly, word line WLI includes single cell transistors at the intersection of word line word line WL1 and bit lines BLO, BL1 and BL2. It will be appreciated that the transistors are identified using the convention that the first number indicates the word line and the second number indicates the bit line (for example transistor MO, O is located at the intersection of word line WL0 and bit line BLO). Each of the memory cell transistors includes a control gate, indicated on the drawing by a CG, a floating gate indicated by FG, drain indicated by D and source indicated by S. As will be appreciated by reference to FIG. 1, all of the source regions are coupled together and further are coupled by line 2 to the ground and erase voltage terminal (G/E). In flash memory array 1, all of the memory cells are erased simultaneously by bringing terminal G/E to VPP (approximately 12 volts), taking the word lines to 0 volts and allowing the bit lines to float. Under these conditions, electrons on the floating gates travel through the gate oxide to the source side of the transistors via Fowler-Nordheim tunneling. A potential problem with this type of array is that the cells may become over erased (that is, have their threshold voltage educed below an acceptable level). Under those circumstances during programming the unselected, over-erased cells draw current which detracts from the programming current required to program the selected cell. Another disadvantage of an array of the type as illustrated by flash memory array 1 is that there is no ability to selectively erase portions of the array. Programming of flash memory array 1 is typically accomplished by channel hot-electron injection into the floating gate from the drain side of the transistor. To illustrate the disadvantage of over-erasure of transistor during program operation, assume that flash memory array 1 has been entirely erased and it is desirable to program transistor MO,O. To program transistor word line MO, O, terminal G/E is placed at 0 volts (0v), word line WL0 is brought to a high voltage (HV) of approximately 12-14 volts and bit line BL0 is raised to 6 to 8 volts. Under these conditions, electrons travel through the gate oxide near the drain region by channel hot-electron injection. Current also flows through source region 3 to terminal G/E during the programming process. Although not selected to be programmed, transistors Ml,O, M2,0 and M3,0 if over-erased, may also slightly conduct and detract from the programming current which is required for programming transistor M0,0. Thus it will be appreciated that flash memory array such as flash memory array I must be carefully engineered to avoid the potential problems which may occur on programming, including the disturbance of unselected cells along the word line and bit lines. And additionally, as pointed out above, flash memory of the type illustrated by array 1 must be entirely erased and no provision is available for erasing less than the entire array.
Referring to FIG. 2, it will be appreciated that flash memory array 8 is in many respects similar to flash memory array 1 of FIG. 1. However, flash memory array 8 incorporates a pass gate transistor (which is also sometimes referred to as a select transistor) for each word line; more particularly, word line WL0 includes pass gate transistor T0, word line WLI includes pass gate transistor Tl, word line WL2 includes pass gate transistor T2 and word line WL3 includes pass gate transistor T3. In flash memory array 8 the transistors associated with word lines WL0 and WLI share in common a source region, indicated by reference character 9, and the transistors associated with word lines WL2 and WL3 share in common the source region indicated by reference character 10. Unlike flash memory array 1, the source regions in flash memory array 8 are not commonly connected. It will also be appreciated by referring to FIG. 2 that the G/E terminal is connected via line lI to the respective drains of pass gate transistors T0-T3. The source regions of pass gate transistors T0-T3 are common with the source region for the cells along the word line to which the gate of the transistor is connector. The architecture of flash memory array 8 is similar to that described in U.S. Pat. No. 4,698,787, issued Oct. 6, 1987 to Mukherjee et al., entitled "Single Transistor Electrically Programmable Memory Device and Method". The inclusion of pass gate transistors T0-T3 provides some protection from the over-erase problems encountered in flash memory array of the type illustrated in FIG. 1. With the architecture of flash memory array 8 it is possible to erase the entire array, which requires two cycles of operation, as will be described hereafter, or erase individual word lines, or erase all the even numbered word lines or all of the odd numbered word lines. However, it is not possible to erase adjacent word lines in a single erase cycle.
To assist in understanding the program and erase operations for flash memory array 8, Table 1 is provided.
TABLE 1 ______________________________________ Signals for Programming and Erasing FLASH MEMORY ARRAY 8 OF FIG. 2 Erasing Transistor Programming Lead M1, 0 Transistor M1, 0 ______________________________________ WL0 VPP+ 0 volts WL1 0 volts VPP+ or VPP WL2 VPP+ 0 volts WL3 0 volts 0 volts BL0 Floating 6-9 volts BL1 Floating Floating BL Floating Floating G/E VPP 0 volts ______________________________________
As will be appreciated by reference to Table 1, to erase transistor M1,0 word line WL0 is brought to VPP+ (typically 13-14 volts) which is required to turn on pass gate transistor T0. Bit line BL0 is floating and ground erase terminal G/E is brought to VPP+. Under these conditions, electrons on the floating gate of transistor M1,0 tunnel by the Fowler-Nordheim phenomenon to the source of transistor M1,0 and the transistor is erased. Other transistors along word line WL1 are similarly erased because node 9 is connected in common. It will be appreciated that erasing transistors on the word line WL1 tends to disturb the transistors on word line WL0 because during the erase process, the control gate of each of the transistors on word line WL0 are at a high voltage and similarly common source region 9 is also at a high voltage since it is coupled to terminal G/E via line 11 and pass gate transistor T0. During the erase of cells on word line WLI, pass gate transistor T0 is conducting and pass gate transistor Tl is not conducting. From the foregoing it will be appreciated that the pass gate transistor on the word line adjacent to the source side of the transistor being erased must be conducting to accomplish erasure of transistors along the word line which is selected for erasure. Similarly to the foregoing situation, to erase transistors along word line WL3, word line WL2 is brought to VPP+, appropriate voltages applied to the bit lines and the erase voltage applied to terminal G/E. Thus in order to erase flash memory array 8 entirely, two cycles of operation are required. More particularly, in the first cycle even numbered word lines are brought high to erase the cells on odd-numbered word lines, and during the second cycle odd numbered word lines are brought high to erase the cells on the even-numbered word lines. If sector erase were to be used with this architecture, accurate and careful control of the word line and G/E voltages would be required to prevent disturb on the unselected sectors. This control would be difficult to achieve in practice.
One approach that has been taken to provide flash and byte erasability for a EEPROM array is disclosed in U.S. Pat. No. 4,949,309 issued Aug. 14, 1990 to Kamesawara K. Rao entitled "EEPROM Utilizing a Single Transistor Per Cell Capable of Both Byte Erase and Flash Erase". This patent is commonly assigned to the assignee of the present application. In the architecture utilized in the Rao patent, portions of the array may be erased on a byte-by-byte basis, or in the alternative the entire array of floating gate transistors can be erased simultaneously. In the circuits disclosed in the Rao patent an erase transistor is provided for every eight floating gate memory cells, and through the application of appropriate potentials to the array, one or more of the bytes may be erased, up to a maximum of all of the bytes in the array. Although this concept and architecture works well, it will be appreciated that a substantial number of erase transistors are required to erase the entire array, which of course decreases the packing density for the memory transistors used in the array.